In integrated circuits, traces or “wires” on various layers are electrically connected to traces on other layers by means of vertical metal “vias” between such layers. Under the conventional art, the pattern of vias between two layers, e.g., wiring or metal layers, is completely defined lithographically by exposing an image of a mask via pattern, etching holes in the separating dielectric, and then filling the holes with metal, e.g., copper.
Unfortunately, due to a variety of factors, including, e.g., small via size and high density of vias, and because of the requirement to align the via pattern to the interacting wire patterns, the via processing steps are among the most lithographically challenging and costly steps in an integrated circuit manufacturing process. Accordingly, the minimum spacing of vias is frequently about 20% larger than a minimum spacing of lines. Thus, a via pattern may frequently limit an achievable line-pattern density of the metal layers they connect.